vhdl.js (2947B)
1 /* 2 Language: VHDL 3 Author: Igor Kalnitsky <igor@kalnitsky.org> 4 Contributors: Daniel C.K. Kho <daniel.kho@tauhop.com>, Guillaume Savaton <guillaume.savaton@eseo.fr> 5 Description: VHDL is a hardware description language used in electronic design automation to describe digital and mixed-signal systems. 6 Website: https://en.wikipedia.org/wiki/VHDL 7 */ 8 9 function vhdl(hljs) { 10 // Regular expression for VHDL numeric literals. 11 12 // Decimal literal: 13 var INTEGER_RE = '\\d(_|\\d)*'; 14 var EXPONENT_RE = '[eE][-+]?' + INTEGER_RE; 15 var DECIMAL_LITERAL_RE = INTEGER_RE + '(\\.' + INTEGER_RE + ')?' + '(' + EXPONENT_RE + ')?'; 16 // Based literal: 17 var BASED_INTEGER_RE = '\\w+'; 18 var BASED_LITERAL_RE = INTEGER_RE + '#' + BASED_INTEGER_RE + '(\\.' + BASED_INTEGER_RE + ')?' + '#' + '(' + EXPONENT_RE + ')?'; 19 20 var NUMBER_RE = '\\b(' + BASED_LITERAL_RE + '|' + DECIMAL_LITERAL_RE + ')'; 21 22 return { 23 name: 'VHDL', 24 case_insensitive: true, 25 keywords: { 26 keyword: 27 'abs access after alias all and architecture array assert assume assume_guarantee attribute ' + 28 'begin block body buffer bus case component configuration constant context cover disconnect ' + 29 'downto default else elsif end entity exit fairness file for force function generate ' + 30 'generic group guarded if impure in inertial inout is label library linkage literal ' + 31 'loop map mod nand new next nor not null of on open or others out package parameter port ' + 32 'postponed procedure process property protected pure range record register reject ' + 33 'release rem report restrict restrict_guarantee return rol ror select sequence ' + 34 'severity shared signal sla sll sra srl strong subtype then to transport type ' + 35 'unaffected units until use variable view vmode vprop vunit wait when while with xnor xor', 36 built_in: 37 'boolean bit character ' + 38 'integer time delay_length natural positive ' + 39 'string bit_vector file_open_kind file_open_status ' + 40 'std_logic std_logic_vector unsigned signed boolean_vector integer_vector ' + 41 'std_ulogic std_ulogic_vector unresolved_unsigned u_unsigned unresolved_signed u_signed ' + 42 'real_vector time_vector', 43 literal: 44 'false true note warning error failure ' + // severity_level 45 'line text side width' // textio 46 }, 47 illegal: '{', 48 contains: [ 49 hljs.C_BLOCK_COMMENT_MODE, // VHDL-2008 block commenting. 50 hljs.COMMENT('--', '$'), 51 hljs.QUOTE_STRING_MODE, 52 { 53 className: 'number', 54 begin: NUMBER_RE, 55 relevance: 0 56 }, 57 { 58 className: 'string', 59 begin: '\'(U|X|0|1|Z|W|L|H|-)\'', 60 contains: [hljs.BACKSLASH_ESCAPE] 61 }, 62 { 63 className: 'symbol', 64 begin: '\'[A-Za-z](_?[A-Za-z0-9])*', 65 contains: [hljs.BACKSLASH_ESCAPE] 66 } 67 ] 68 }; 69 } 70 71 module.exports = vhdl;